The specification for the course is shown on the left. This is a modified version of the AQA AS Computer Science specification in which some parts have been made more granular. For each part of the specification, statistics are shown for how many past papers it was examined in and the percentage of the total of all past marks that it makes up (where a question covers multiple parts of a specification, marks are divided equally between them for the purpose of this calculation). You can also click to view matching flashcards and past paper questions which will be shown on the right.

Paper 2 covers sections 5-9 of the AQA AS Computer Science specification.

5 Fundamentals of data representation

5.1 Number systems

5.1.1 Natural numbers

ReferenceContentAdditional informationQuestions
5.1.1.1
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Be familiar with the concept of a natural number and the set ℕ of natural numbers (including zero).

ℕ = {0, 1, 2, 3, …}

Exams: 8 / 16Marks: 0.38%Questions: 9

5.1.2 Integer numbers

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5.1.2.1
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Be familiar with the concept of an integer and the set ℤ of integers.

ℤ = { …, -3, -2, -1, 0, 1, 2, 3, … }

Exams: 7 / 16Marks: 0.24%Questions: 7

5.1.3 Rational numbers

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5.1.3.1
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Be familiar with the concept of a rational number and the set ℚ of rational numbers, and that this set includes the integers.

ℚ is the set of numbers that can be written as fractions (ratios of integers). Since a number such as 7 can be written as 7/1, all integers are rational numbers.

Exams: 5 / 16Marks: 0.28%Questions: 7

5.1.4 Irrational numbers

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5.1.4.1
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Be familiar with the concept of an irrational number.

An irrational number is one that cannot be written as a fraction, for example √2.

Exams: 8 / 16Marks: 0.47%Questions: 8

5.1.5 Real numbers

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5.1.5.1
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Be familiar with the concept of a real number and the set ℝ of real numbers, which includes the natural numbers, the rational numbers, and the irrational numbers.

ℝ is the set of all 'possible real world quantities'.

Exams: 6 / 16Marks: 0.28%Questions: 6

5.1.6 Ordinal numbers

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5.1.6.1
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Be familiar with the concept of ordinal numbers and their use to describe the numerical positions of objects.

When objects are placed in order, ordinal numbers are used to tell their position. For example, if we have a well-ordered set S = {'a', 'b', 'c', 'd'}, then 'a' is the 1st object, 'b' the 2nd, and so on.

Exams: 2 / 16Marks: 0.21%Questions: 2

5.1.7 Counting and measurement

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5.1.7.1
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Be familiar with the use of natural numbers for counting.

Exams: 2 / 16Marks: 0.14%Questions: 2
5.1.7.2
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Be familiar with the use of real numbers for measurement.

Exams: 3 / 16Marks: 0.21%Questions: 3

5.2 Number bases

5.2.1 Number base

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5.2.1.1
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Be familiar with the concept of a number base, in particular:

  • decimal (base 10)
  • binary (base 2)
  • hexadecimal (base 16)

Students should be familiar with expressing a number's base using a subscript as follows:

  • Base 10: Number10, eg 6710
  • Base 2: Number2, eg 100110112
  • Base 16: Number16, eg AE16
Exams: 0 / 16Marks: 0.00%Questions: 0
5.2.1.2
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Convert between decimal, binary and hexadecimal number bases.

Exams: 9 / 16Marks: 0.86%Questions: 11
5.2.1.3
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Be familiar with, and able to use, hexadecimal as a shorthand for binary and to understand why it is used in this way.

Exams: 4 / 16Marks: 0.29%Questions: 4

5.3 Units of information

5.3.1 Bits and bytes

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5.3.1.1
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Know that the bit is the fundamental unit of information.

A bit is either 0 or 1.

Exams: 0 / 16Marks: 0.00%Questions: 0
5.3.1.2
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Know that a byte is a group of 8 bits.

Exams: 2 / 16Marks: 0.07%Questions: 2
5.3.1.3
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Know that 2n different values can be represented with n bits.

For example, 3 bits can be configured in 23 = 8 different ways: 000, 001, 010, 011, 100, 101, 110, 111.

Exams: 4 / 16Marks: 0.18%Questions: 4

5.3.2 Units

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5.3.2.1
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Know the names, symbols and corresponding powers of 10 for the decimal prefixes:

  • kilo, k - 103
  • mega, M - 106
  • giga, G - 109
  • tera, T - 1012
Exams: 2 / 16Marks: 0.11%Questions: 2
5.3.2.2
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Know the names, symbols and corresponding powers of 2 for the binary prefixes:

  • kibi, Ki - 210
  • mebi, Mi - 220
  • gibi, Gi - 230
  • tebi, Ti - 240
Exams: 1 / 16Marks: 0.04%Questions: 1
5.3.2.3
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Know that quantities of bytes can be described using binary prefixes representing powers of 2 or using decimal prefixes representing powers of 10, eg one kibibyte is written as 1KiB = 210 B and one kilobyte is written as 1 kB = 103 B.

Historically the terms kilobyte, megabyte, etc have often been used when kibibyte, mebibyte, etc are meant.

Exams: 3 / 16Marks: 0.18%Questions: 3

5.4 Binary number system

5.4.1 Unsigned binary

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5.4.1.1
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Know the difference between unsigned binary and signed binary.

Students are expected to be able to convert between unsigned binary and decimal and vice versa.

Exams: 2 / 16Marks: 0.07%Questions: 2
5.4.1.2
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Know that in unsigned binary the minimum and maximum values for a given number of bits, n, are 0 and 2n - 1 respectively.

Exams: 1 / 16Marks: 0.14%Questions: 1

5.4.2 Unsigned binary arithmetic

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5.4.2.1
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Be able to add two unsigned binary integers.

Exams: 5 / 16Marks: 0.43%Questions: 5
5.4.2.2
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Be able to multiply two unsigned binary integers.

Exams: 3 / 16Marks: 0.43%Questions: 3

5.4.3 Signed binary using two's complement

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5.4.3.1
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Know that signed binary can be used to represent negative integers and that one possible coding scheme is two's complement.

This is the only representation of negative integers that will be examined. Students are expected to be able to convert between signed binary and decimal and vice versa.

Exams: 1 / 16Marks: 0.07%Questions: 1
5.4.3.2
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Know how to represent negative and positive integers in two's complement.

Exams: 0 / 16Marks: 0.00%Questions: 0
5.4.3.3
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Know how to perform subtraction using two's complement.

Exams: 5 / 16Marks: 0.64%Questions: 5
5.4.3.4
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Know how to calculate the range of a given number of bits, n.

Exams: 2 / 16Marks: 0.14%Questions: 2

5.4.4 Numbers with a fractional part

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5.4.4.1
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Know how numbers with a fractional part can be represented in fixed point form in binary in a given number of bits.

Exams: 1 / 16Marks: 0.07%Questions: 1
5.4.4.2
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Be able to convert decimal to fixed point binary of a given number of bits.

Exams: 1 / 16Marks: 0.14%Questions: 1
5.4.4.3
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Be able to convert fixed point binary to decimal of a given number of bits.

Exams: 4 / 16Marks: 0.57%Questions: 4

5.5 Information coding systems

5.5.1 Character form of a decimal digit

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5.5.1.1
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Differentiate between the character code representation of a decimal digit and its pure binary representation.

Exams: 3 / 16Marks: 0.21%Questions: 3

5.5.2 ASCII and Unicode

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5.5.2.1
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Describe ASCII and Unicode coding systems for coding character data.

Exams: 1 / 16Marks: 0.07%Questions: 1
5.5.2.2
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Explain why Unicode was introduced.

Exams: 3 / 16Marks: 0.43%Questions: 3

5.5.3 Error checking and correction

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5.5.3.1
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Describe and explain the use of parity bits.

Exams: 8 / 16Marks: 0.89%Questions: 9
5.5.3.2
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Describe and explain the use of majority voting.

Exams: 4 / 16Marks: 0.57%Questions: 4
5.5.3.3
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Describe and explain the use of check digits.

Exams: 1 / 16Marks: 0.14%Questions: 1
5.5.3.4
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Evaluate the use of parity bits, majority voting and check digits

Exams: 5 / 16Marks: 0.57%Questions: 5

5.6 Representing images, sound and other data

5.6.1 Bit patterns, images, sound and other data

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5.6.1.1
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Describe how bit patterns may represent other forms of data, including graphics and sound.

Exams: 0 / 16Marks: 0.00%Questions: 0

5.6.2 Analogue and digital

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5.6.2.1
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Understand the difference between analogue and digital:

  • data
  • signals
Exams: 3 / 16Marks: 0.43%Questions: 3

5.6.3 Analogue/digital conversion

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5.6.3.1
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Describe the principles of operation of an analogue to digital converter (ADC).

Exams: 5 / 16Marks: 0.86%Questions: 5
5.6.3.2
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Describe the principles of operation of a digital to analogue converter (DAC).

Exams: 1 / 16Marks: 0.07%Questions: 1

5.6.4 Bitmapped graphics

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5.6.4.1
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Explain how bitmaps are represented.

Exams: 0 / 16Marks: 0.00%Questions: 0
5.6.4.2
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Explain resolution.

Resolution is expressed as number of dots per inch where a dot is a pixel.

Exams: 0 / 16Marks: 0.00%Questions: 0
5.6.4.3
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Know that colour depth is the number of bits stored for each pixel.

Exams: 2 / 16Marks: 0.14%Questions: 2
5.6.4.4
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Know that the size of an image in pixels is width of image in pixels × height of image in pixels.

The size of an image is also alternatively sometimes described as the resolution of an image.

Exams: 0 / 16Marks: 0.00%Questions: 0
5.6.4.5
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Calculate storage requirements for bitmapped images and be aware that bitmap image files may also contain metadata.

Ignoring metadata, storage requirements = size in pixels x colour depth where size in pixels is width in pixels x height in pixels.

Exams: 8 / 16Marks: 1.36%Questions: 9
5.6.4.6
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Be familiar with typical metadata.

eg width, height, colour depth.

Exams: 1 / 16Marks: 0.07%Questions: 1

5.6.5 Digital representation of sound

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5.6.5.1
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Describe the digital representation of sound.

Exams: 0 / 16Marks: 0.00%Questions: 0
5.6.5.2
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Understand sample resolution and its effect on the quality of audio recordings.

Exams: 4 / 16Marks: 0.43%Questions: 5
5.6.5.3
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Understand sampling rate and its effect on the quality of audio recordings.

Exams: 2 / 16Marks: 0.14%Questions: 2
5.6.5.4
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Know Nyquist's theorem.

Exams: 4 / 16Marks: 0.43%Questions: 4
5.6.5.5
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Calculate sound sample sizes in bytes.

Exams: 8 / 16Marks: 1.43%Questions: 8

5.6.6 Musical Instrument Digital Interface (MIDI)

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5.6.6.1
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Describe the purpose of MIDI and the use of event messages in MIDI.

Exams: 3 / 16Marks: 0.43%Questions: 3
5.6.6.2
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Describe the advantages of using MIDI files for representing music.

Exams: 5 / 16Marks: 0.71%Questions: 5

5.6.7 Data compression

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5.6.7.1
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Know why images and sound files are often compressed and that other files, such as text files, can also be compressed.

Exams: 1 / 16Marks: 0.07%Questions: 1
5.6.7.2
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Understand the difference between lossless and lossy compression and explain the advantages and disadvantages of each.

Exams: 5 / 16Marks: 0.86%Questions: 5
5.6.7.3
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Explain the principles behind run length encoding (RLE) for lossless compression.

Exams: 4 / 16Marks: 0.79%Questions: 6
5.6.7.4
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Explain the principles behind dictionary-based methods for lossless compression.

Exams: 2 / 16Marks: 0.43%Questions: 3

5.6.8 Encryption

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5.6.8.1
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Understand what is meant by encryption and be able to define it.

Caesar and Vernam ciphers are at opposite extremes. One offers perfect security, the other doesn't. Between these two types are ciphers that are computationally secure – see below. Students will be assessed on the two types. Ciphers other than Caesar may be used to assess students' understanding of the principles involved. These will be explained and be similar in terms of computational complexity.

Exams: 1 / 16Marks: 0.07%Questions: 1
5.6.8.2
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Be familiar with the term cipher.

Exams: 0 / 16Marks: 0.00%Questions: 0
5.6.8.3
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Be familiar with the term plaintext.

Exams: 0 / 16Marks: 0.00%Questions: 0
5.6.8.4
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Be familiar with the term ciphertext.

Exams: 0 / 16Marks: 0.00%Questions: 0
5.6.8.5
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Be familiar with Caesar cipher and be able to apply it to encrypt a plaintext message and decrypt a ciphertext.

Exams: 6 / 16Marks: 0.64%Questions: 6
5.6.8.6
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Be able to explain why Caesar cipher is easily cracked.

Exams: 3 / 16Marks: 0.36%Questions: 4
5.6.8.7
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Be familiar with Vernam cipher or one-time pad and be able to apply it to encrypt a plaintext message and decrypt a ciphertext.

Since the key k is chosen uniformly at random, the ciphertext c is also distributed uniformly. The key k must be used once only. The key k is known as a one-time pad.

Exams: 4 / 16Marks: 0.75%Questions: 4
5.6.8.8
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Explain why Vernam cipher is considered as a cypher with perfect security.

Exams: 4 / 16Marks: 0.43%Questions: 4
5.6.8.9
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Compare Vernam cipher with ciphers that depend on computational security.

Vernam cipher is the only one to have been mathematically proved to be completely secure. The worth of all other ciphers ever devised is based on computational security. In theory, every cryptographic algorithm except for Vernam cipher can be broken, given enough ciphertext and time.

Exams: 1 / 16Marks: 0.07%Questions: 1

6 Fundamentals of computer systems

6.1 Hardware and software

6.1.1 Relationship between hardware and software

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6.1.1.1
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Define the term hardware.

Exams: 1 / 16Marks: 0.07%Questions: 1
6.1.1.2
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Define the term software.

Exams: 2 / 16Marks: 0.14%Questions: 2
6.1.1.3
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Understand the relationship between hardware and software.

Exams: 1 / 16Marks: 0.07%Questions: 1

6.1.2 Classification of software

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6.1.2.1
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Explain what is meant by system software.

Exams: 3 / 16Marks: 0.21%Questions: 3
6.1.2.2
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Explain what is meant by application software.

Exams: 2 / 16Marks: 0.14%Questions: 2
6.1.2.3
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Understand the need for, and attributes of, different types of software.

Exams: 0 / 16Marks: 0.00%Questions: 0

6.1.3 System software

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6.1.3.1
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Know that system software includes operating systems (OSs), utility programs, libraries and translators (compiler, assembler, interpreter).

Exams: 4 / 16Marks: 0.43%Questions: 4
6.1.3.2
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Understand the need for, and functions of operating systems (OSs).

Exams: 1 / 16Marks: 0.07%Questions: 1
6.1.3.3
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Understand the need for, and functions of utility programs.

Exams: 2 / 16Marks: 0.21%Questions: 2
6.1.3.4
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Understand the need for, and functions of libraries.

Exams: 1 / 16Marks: 0.14%Questions: 1
6.1.3.5
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Understand the need for, and functions of translators (compiler, assembler, interpreter).

Exams: 1 / 16Marks: 0.29%Questions: 1

6.1.4 Role of an operating system (OS)

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6.1.4.1
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Understand that a role of the operating system is to hide the complexities of the hardware.

Exams: 2 / 16Marks: 0.14%Questions: 2
6.1.4.2
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Know that the OS handles resource management, managing hardware to allocate processors, memories and I/O devices among competing processes.

Exams: 5 / 16Marks: 0.50%Questions: 5

6.2 Classification of programming languages

6.2.1 Classification of programming languages

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6.2.1.1
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Show awareness of the development of types of programming languages and their classification into low- and high-level languages.

Exams: 1 / 16Marks: 0.07%Questions: 1
6.2.1.2
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Know that low-level languages are considered to be:

  • machine-code
  • assembly language
Exams: 1 / 16Marks: 0.07%Questions: 1
6.2.1.3
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Know that high-level languages include imperative high-level language.

Exams: 2 / 16Marks: 0.14%Questions: 2
6.2.1.4
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Describe machine-code language and assembly language.

Exams: 2 / 16Marks: 0.21%Questions: 2
6.2.1.5
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Understand the advantages and disadvantages of machine-code and assembly language programming compared with high-level language programming.

Exams: 6 / 16Marks: 1.50%Questions: 6
6.2.1.6
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Explain the term 'imperative high-level language' and its relationship to low-level languages.

Exams: 1 / 16Marks: 0.14%Questions: 1

6.3 Types of program translator

6.3.1 Types of program translator

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6.3.1.1
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Understand the role of assemblers.

Exams: 1 / 16Marks: 0.07%Questions: 1
6.3.1.2
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Understand the role of compilers.

Exams: 1 / 16Marks: 0.07%Questions: 1
6.3.1.3
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Understand the role of interpreters.

Exams: 0 / 16Marks: 0.00%Questions: 0
6.3.1.4
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Explain the differences between compilation and interpretation. Describe situations in which each would be appropriate.

Exams: 3 / 16Marks: 0.71%Questions: 3
6.3.1.5
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Explain why an intermediate language such as bytecode is produced as the final output by some compilers and how it is subsequently used.

Exams: 2 / 16Marks: 0.43%Questions: 4
6.3.1.6
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Understand the difference between source and object (executable) code.

Exams: 0 / 16Marks: 0.00%Questions: 0

6.4 Logic gates

6.4.1 Logic gates

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6.4.1.1
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Construct truth tables for the NOT logic gate.

Students should know and be able to use ANSI/IEEE standard 91-1984 Distinctive shape logic gate symbols for these logic gates.

Exams: 0 / 16Marks: 0.00%Questions: 0
6.4.1.2
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Construct truth tables for the AND logic gate.

Exams: 0 / 16Marks: 0.00%Questions: 0
6.4.1.3
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Construct truth tables for the OR logic gate.

Exams: 2 / 16Marks: 0.06%Questions: 2
6.4.1.4
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Construct truth tables for the XOR logic gate.

Exams: 4 / 16Marks: 0.24%Questions: 4
6.4.1.5
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Construct truth tables for the NAND logic gate.

Exams: 4 / 16Marks: 0.25%Questions: 4
6.4.1.6
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Construct truth tables for the NOR logic gate.

Exams: 3 / 16Marks: 0.17%Questions: 3
6.4.1.7
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Be familiar with drawing and interpreting logic gate circuit diagrams involving one or more of the above gates.

Exams: 6 / 16Marks: 1.14%Questions: 7
6.4.1.8
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Complete a truth table for a given logic gate circuit.

Exams: 10 / 16Marks: 1.86%Questions: 10
6.4.1.9
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Write a Boolean expression for a given logic gate circuit.

Exams: 5 / 16Marks: 0.79%Questions: 5
6.4.1.10
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Draw an equivalent logic gate circuit for a given Boolean expression.

Exams: 4 / 16Marks: 0.93%Questions: 4

6.5 Boolean algebra

6.5.1 Using Boolean algebra

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6.5.1.1
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Be familiar with the use of Boolean identities and De Morgan's laws to manipulate and simplify Boolean expressions.

Exams: 15 / 16Marks: 4.71%Questions: 20

7 Fundamentals of computer organisation and architecture

7.1 Internal hardware components of a computer

7.1.1 Internal hardware components of a computer

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7.1.1.1
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Have an understanding and knowledge of the basic internal components of a computer system.

Although exam questions about specific machines will not be asked, it might be useful to base this section on the machines used at the centre.

Exams: 0 / 16Marks: 0.00%Questions: 0
7.1.1.2
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Understand the role of the processor.

Exams: 1 / 16Marks: 0.03%Questions: 1
7.1.1.3
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Understand the role of main memory.

Exams: 2 / 16Marks: 0.17%Questions: 2
7.1.1.4
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Understand the role of the address bus.

Exams: 5 / 16Marks: 0.41%Questions: 6
7.1.1.5
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Understand the role of the data bus.

Exams: 4 / 16Marks: 0.30%Questions: 4
7.1.1.6
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Understand the role of the control bus.

Exams: 2 / 16Marks: 0.17%Questions: 2
7.1.1.7
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Understand the role of I/O controllers.

Exams: 2 / 16Marks: 0.17%Questions: 2
7.1.1.8
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Be able to explain the difference between von Neumann and Harvard architectures and describe where each is typically used.

Embedded systems such as digital signal processing (DSP) systems use Harvard architecture processors extensively. Von Neumann architecture is used extensively in general purpose computing systems.

Exams: 4 / 16Marks: 0.64%Questions: 5
7.1.1.9
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Understand the concept of addressable memory.

Exams: 0 / 16Marks: 0.00%Questions: 0

7.2 The stored program concept

7.2.1 The meaning of the stored program concept

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7.2.1.1
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Be able to describe the stored program concept: machine code instructions stored in main memory are fetched and executed serially by a processor that performs arithmetic and logical operations.

Exams: 5 / 16Marks: 0.57%Questions: 5

7.3 Structure and role of the processor and its components

7.3.1 The processor and its components

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7.3.1.1
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Explain the role and operation of the arithmetic logic unit.

Exams: 1 / 16Marks: 0.07%Questions: 1
7.3.1.2
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Explain the role and operation of the control unit.

Exams: 1 / 16Marks: 0.21%Questions: 1
7.3.1.3
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Explain the role and operation of the clock.

Exams: 0 / 16Marks: 0.00%Questions: 0
7.3.1.4
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Explain the role and operation of general-purpose registers.

Exams: 2 / 16Marks: 0.14%Questions: 2
7.3.1.5
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Explain the role and operation of the program counter.

Exams: 0 / 16Marks: 0.00%Questions: 0
7.3.1.6
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Explain the role and operation of the current instruction register.

Exams: 1 / 16Marks: 0.05%Questions: 1
7.3.1.7
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Explain the role and operation of the memory address register.

Exams: 1 / 16Marks: 0.04%Questions: 1
7.3.1.8
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Explain the role and operation of the memory buffer register.

Exams: 2 / 16Marks: 0.08%Questions: 2
7.3.1.9
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Explain the role and operation of the status register.

Exams: 1 / 16Marks: 0.14%Questions: 1

7.3.2 The Fetch-Execute cycle and the role of registers within it

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7.3.2.1
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Explain how the Fetch-Execute cycle is used to execute machine code programs, including the stages in the cycle (fetch, decode, execute) and details of registers used.

Exams: 7 / 16Marks: 2.10%Questions: 8

7.3.3 The processor instruction set

ReferenceContentAdditional informationQuestions
7.3.3.1
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Understand the term 'processor instruction set' and know that an instruction set is processor specific.

Exams: 2 / 16Marks: 0.29%Questions: 2
7.3.3.2
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Know that instructions consist of an opcode and one or more operands (value, memory address or register).

A simple model will be used in which the addressing mode will be incorporated into the bits allocated to the opcode so the latter defines both the basic machine operation and the addressing mode. Students will not be expected to define opcode, only interpret opcodes in the given context of a question.

For example, 4 bits have been allocated to the opcode (3 bits for basic machine operation, eg ADD, and 1 bit for the addressing mode). 4 bits have been allocated to the operand, making the instruction, opcode + operand, 8 bits in length. In this example, 16 different opcodes are possible (24 = 16).

OpcodeOperand
Basic Machine OperationAddressing Mode
00100101
Exams: 4 / 16Marks: 0.39%Questions: 4

7.3.4 Addressing modes

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7.3.4.1
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Understand and apply immediate addressing.

Immediate addressing: the operand is the datum.

Exams: 3 / 16Marks: 0.18%Questions: 3
7.3.4.2
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Understand and apply direct addressing.

Direct addressing: the operand is the address of the datum. Address to be interpreted as meaning either main memory or register.

Exams: 2 / 16Marks: 0.11%Questions: 2

7.3.5 Machine-code/assembly language operations

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7.3.5.1
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Understand and apply the basic machine-code operations of:

  • load
  • add
  • subtract
  • store
  • branching (conditional and unconditional)
  • compare
  • logical bitwise operators (AND, OR, NOT, XOR)
  • logical
  • shift right
  • shift left
  • halt

Use the basic machine-code operations above when machine-code instructions are expressed in mnemonic form—assembly language, using immediate and direct addressing.

Exams: 16 / 16Marks: 6.54%Questions: 28

7.3.6 Factors affecting processor performance

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7.3.6.1
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Explain the effect on processor performance of multiple cores.

Exams: 2 / 16Marks: 0.19%Questions: 2
7.3.6.2
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Explain the effect on processor performance of cache memory.

Exams: 4 / 16Marks: 0.57%Questions: 4
7.3.6.3
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Explain the effect on processor performance of clock speed.

Exams: 4 / 16Marks: 0.42%Questions: 4
7.3.6.4
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Explain the effect on processor performance of word length.

Exams: 3 / 16Marks: 0.28%Questions: 3
7.3.6.5
View

Explain the effect on processor performance of address bus width.

Exams: 3 / 16Marks: 0.35%Questions: 3
7.3.6.6
View

Explain the effect on processor performance of data bus width.

Exams: 4 / 16Marks: 0.35%Questions: 4

7.4 External hardware devices

7.4.1 Input and output devices

ReferenceContentAdditional informationQuestions
7.4.1.1
View

Know the main characteristics, purpose and suitability of barcode readers and understand their principles of operation.

Exams: 2 / 16Marks: 0.29%Questions: 2
7.4.1.2
View

Know the main characteristics, purpose and suitability of digital cameras and understand their principles of operation.

Exams: 3 / 16Marks: 0.68%Questions: 3
7.4.1.3
View

Know the main characteristics, purpose and suitability of laser printers and understand their principles of operation.

Exams: 2 / 16Marks: 0.96%Questions: 3
7.4.1.4
View

Know the main characteristics, purpose and suitability of RFID and understand their principles of operation.

Exams: 5 / 16Marks: 1.71%Questions: 7

7.4.2 Secondary storage devices

ReferenceContentAdditional informationQuestions
7.4.2.1
View

Explain the need for secondary storage within a computer system.

Exams: 1 / 16Marks: 0.14%Questions: 1
7.4.2.2
View

Know the main characteristics, purposes, suitability and understand the principles of operation of the hard disk.

Exams: 1 / 16Marks: 0.86%Questions: 1
7.4.2.3
View

Know the main characteristics, purposes, suitability and understand the principles of operation of the optical disk.

Exams: 2 / 16Marks: 0.50%Questions: 2
7.4.2.4
View

Know the main characteristics, purposes, suitability and understand the principles of operation of the solid-state disk (SSD).

SSD = NAND flash memory + a controller that manages pages, and blocks and complexities of writing. Based on floating gate transistors that trap and store charge. A block, made up of many pages, cannot overwrite pages; a page has to be erased before it can be written to but technology requires the whole block to be erased. Lower latency and faster transfer speeds than a magnetic disk drive.

Exams: 4 / 16Marks: 0.93%Questions: 4
7.4.2.5
View

Compare the capacity and speed of access of various media and make a judgement about their suitability for different applications.

Exams: 5 / 16Marks: 0.79%Questions: 5

8 Consequences of uses of computing

8.1 Individual (moral), social (ethical), legal and cultural issues and opportunities

ReferenceContentAdditional informationQuestions
8.1.1
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Show awareness of current individual (moral), social (ethical), legal and cultural opportunities and risks of computing.

Understand that:

  • developments in computer science and digital technologies have dramatically altered the shape of communications and information flows in societies, enabling massive transformations in the capacity to:
    • monitor behaviour
    • amass and analyse personal information
    • distribute, publish, communicate and disseminate personal information
  • computer scientists and software engineers therefore have power, as well as the responsibilities that go with it, in the algorithms that they devise and the code that they deploy.
  • software and their algorithms embed moral and cultural values.
  • the issue of scale, for software the whole world over, creates potential for individual computer scientists and software engineers to produce great good, but with it comes the ability to cause great harm.

Be able to discuss the challenges facing legislators in the digital age.

Teachers may wish to employ two very powerful techniques, hypotheticals and case studies, to engage students in the issues.

Hypotheticals allow students to isolate quickly important ethical principles in an artificially simplified context. For example, a teacher might ask students to explain and defend how, as a Google project manager, they would evaluate a proposal to bring Google's Street View technology to a remote African village. What questions should be asked? Who should be consulted? What benefits, risks and safeguards considered? What are the trade-offs?

Case studies allow students to confront the tricky interplay between the sometimes competing ethical values and principles relevant in real world settings. For example, the Google Street View case might be used to tease out the ethical conflicts between individual and cultural expectations, the principle of informed consent, Street View's value as a service, its potential impact on human perceptions and behaviours, and its commercial value to Google and its shareholders.

There are many resources available on the Internet to support teaching of this topic.

Exams: 12 / 16Marks: 5.42%Questions: 12

9 Fundamentals of communication and networking

9.1 Communication

9.1.1 Communication methods

ReferenceContentAdditional informationQuestions
9.1.1.1
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Define serial transmission methods.

Exams: 1 / 16Marks: 0.07%Questions: 1
9.1.1.2
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Define parallel transmission methods.

Exams: 2 / 16Marks: 0.21%Questions: 2
9.1.1.3
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Discuss the advantages of serial over parallel transmission.

Exams: 4 / 16Marks: 0.79%Questions: 4
9.1.1.4
View

Define and compare synchronous and asynchronous data transmission.

Exams: 3 / 16Marks: 0.43%Questions: 4
9.1.1.5
View

Describe the purpose of start and stop bits in asynchronous data transmission.

Exams: 4 / 16Marks: 0.39%Questions: 5

9.1.2 Communication basics

ReferenceContentAdditional informationQuestions
9.1.2.1
View

Define baud rate.

Exams: 2 / 16Marks: 0.14%Questions: 2
9.1.2.2
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Define bit rate.

Exams: 2 / 16Marks: 0.14%Questions: 2
9.1.2.3
View

Define bandwidth.

Exams: 4 / 16Marks: 0.30%Questions: 4
9.1.2.4
View

Define latency.

Exams: 3 / 16Marks: 0.16%Questions: 3
9.1.2.5
View

Define protocol.

Exams: 3 / 16Marks: 0.29%Questions: 3
9.1.2.6
View

Differentiate between baud rate and bit rate.

Bit rate can be higher than baud rate if more than one bit is encoded in each signal change.

Exams: 4 / 16Marks: 0.23%Questions: 4
9.1.2.7
View

Understand the relationship between bit rate and bandwidth.

Bit rate is directly proportionate to bandwidth.

Exams: 4 / 16Marks: 0.23%Questions: 4

9.2 Networking

9.2.1 Network topology

ReferenceContentAdditional informationQuestions
9.2.1.1
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Understand and explain the operation of a physical star topology.

Exams: 2 / 16Marks: 0.29%Questions: 2
9.2.1.2
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Understand and explain the operation of a logical bus network topology.

A network physically wired in star topology can behave logically as a bus network by using a bus protocol and appropriate physical switching.

Exams: 2 / 16Marks: 0.36%Questions: 2
9.2.1.3
View

Differentiate between the physical star topology and the logical bus network topology.

Exams: 3 / 16Marks: 0.36%Questions: 3

9.2.2 Types of networking between hosts

ReferenceContentAdditional informationQuestions
9.2.2.1
View

Explain peer-to-peer networking and describe situations where it might be used.

In a peer-to-peer network, each computer has equal status.

Exams: 5 / 16Marks: 0.89%Questions: 6
9.2.2.2
View

Explain client-server networking and describe situations where it might be used.

In a client-server network, most computers are nominated as clients and one or more as servers. The clients request services from the servers, which provide these services, for example file server, email server.

Exams: 5 / 16Marks: 0.68%Questions: 5

9.2.3 Wireless networking

ReferenceContentAdditional informationQuestions
9.2.3.1
View

Explain the purpose of WiFi.

A wireless local area network that is based on international standards.

Used to enable devices to connect to a network wirelessly.

Exams: 2 / 16Marks: 0.28%Questions: 2
9.2.3.2
View

Be familiar with the components required for wireless networking.

  • Wireless network adapter
  • Wireless access point
Exams: 1 / 16Marks: 0.07%Questions: 1
9.2.3.3
View

Be familiar with the purpose of Service Set Identifier (SSID).

Exams: 3 / 16Marks: 0.29%Questions: 3
9.2.3.4
View

Be familiar with how wireless networks are secured using WPA (Wifi Protected Access)/WPA2.

Exams: 4 / 16Marks: 0.43%Questions: 4
9.2.3.5
View

Be familiar with how wireless networks are secured by disabling SSID (Service Set Identifier) broadcasting.

Exams: 6 / 16Marks: 0.65%Questions: 6
9.2.3.6
View

Be familiar with how wireless networks are secured using a MAC (Media Access Control) address allow list.

Exams: 6 / 16Marks: 0.79%Questions: 6
9.2.3.7
View

Explain the wireless protocol Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) with and without Request to Send/Clear to Send (RTS/CTS).

Exams: 3 / 16Marks: 1.14%Questions: 3

No flashcards added yet.

AS-Level2022June8.1tableDiagram3 marks

The fetch-execute cycle involves the Current Instruction Register (CIR), Control Unit, Memory Address Register (MAR), Memory Buffer Register (MBR) and Program Counter (PC).

Figure 6 lists four events that can take place during one cycle of the fetch-execute cycle. The events are labelled A to D.

Some events that take place during the fetch-execute cycle are not listed.

Put these events in the order they would occur in the fetch-execute cycle when an ADD instruction is executed.

Write the numbers 1 to 4 beside each description in Figure 6 to indicate the order in which the events occur. The number 1 should be used to indicate the event that would happen first.

Figure 6

DescriptionOrder (1 to 4)
A The contents of the MBR are copied to the CIR.
B The contents of the PC are copied to the MAR.
C The Control Unit decodes the contents of the CIR.
D The result of the calculation is stored.
  • B The contents of the PC are copied to the MAR. (1);
  • A The contents of the MBR are copied to the CIR. (2);
  • C The Control Unit decodes the contents of the CIR. (3);
  • D The result of the calculation is stored. (4);
  • 3 marks for all correct;
  • 2 marks for two correct;
  • 1 mark for one correct;
  • R. Labels used more than once.
AS-Level2020June6.5open8 marks

Describe four steps that a processor goes through during the fetch stage of the Fetch-Execute cycle. You must explain the purpose of each step.

DescriptionExplanation
Contents of the Program Counter / PC transferred to the Memory Address Register / MARso that the PC can be updated // to enable the memory address to be transferred along the address bus/to the memory
Contents of MAR placed onto address busso the correct location in the main memory will be accessed
Contents of addressed memory location/value received on data bus loaded into the Memory Buffer Register / MBRnot all fetches will be for instructions so cannot be loaded directly into Current Instruction Register / CIR // the value will only be present transiently on the bus so must be stored in a register // the MBR is used to cope with the speed difference between the processor and the main memory
(Contents of) PC is incrementedso that the next instruction in the sequence can be fetched
The contents of the MBR is copied to the CIRso that if data is fetched/written during the execute phase it does not overwrite the instruction // because the control unit uses the instruction from the CIR

A. Memory Data Register/MDR for Memory Buffer Register/MBR
Max 4 for descriptions
Max 4 for explanations
Max 8

AS-Level2017June6.3open6 marks

Describe, using full sentences, the steps involved in the Fetch-Execute cycle for the von Neumann architecture. Your description should cover the fetch, decode and execute stages and must clearly state which of the three sections each step falls in.

Level of response question

LevelDescriptionMark Range
3At least five of the steps of the cycle have been correctly identified in order/the steps are all in correct order and covering all three of the stages (fetch, decode, execute). For the top mark in this level thorough understanding of how the cycle works is evident.5-6
2At least three steps of the cycle have been identified in order, covering at least two of the stages (fetch, decode, execute). Some understanding of how the cycle works is evident.3-4
1At least one step of the cycle have been identified, covering at least one stage (fetch, decode or execute). The order of the steps may not be correct. Little understanding of how the cycle works is evident.1-2

Points may include:

Fetch:

  • Contents of Program Counter / PC transferred to Memory Address Register / MAR
  • Address bus used to transfer this address to main memory
  • Transfer of content uses the data bus
  • Contents of addressed memory location loaded into the Memory Buffer Register / MBR
  • Increment (contents of) Program Counter / PC A. at any part of fetch process after transferring PC to MAR
  • Increment Program Counter / PC and fetch simultaneously
  • Contents of MBR copied to CIR

Decode:

  • Decode instruction held by the (Current) Instruction Register / (C)IR
  • The control unit decodes the instruction
  • Instruction split into opcode and operand

Execute:

  • If necessary, data is fetched
  • If necessary, data is stored in memory
  • The opcode identifies the type of operation/instruction to be performed (by the processor)
  • Result (may be) stored in register/accumulator
  • The operation (identified by the opcode) is performed by the processor. A. ALU
  • Status register updated
  • If jump / branch required Program Counter/PC is updated

NE. Register notation
A. Memory Data Register/MDR for Memory Buffer Register/MBR
I. Incorrect headings

A-Level2023June4.1open12 marks

Describe how the fetch-execute cycle is used to carry out machine code instructions and how the hardware of a computer could be improved so that programs can be executed more quickly.

Your response should include a description of what happens during each stage of the fetch-execute cycle.

Level Descriptors

LevelDescriptionMark Range
4A line of reasoning has been followed to produce a coherent, relevant, substantiated and logically-structured response. The response covers both areas indicated in the guidance below and, in each area, there is sufficient detail to show that the student has a good level of understanding.10–12
3A line of reasoning has been followed to produce a coherent, relevant, substantiated and logically structured response which shows a good level of understanding of at least one area indicated in the guidance below and some understanding of the other area.7–9
2A limited attempt has been made to follow a line of reasoning and the response has a mostly logical structure. A good level of understanding has been shown of one area or some understanding of both areas.4–6
1A few relevant points have been made but there is no evidence that a line of reasoning has been followed. There is insufficient evidence of a good level of understanding of either of the two areas.1–3

Indicative Content

Area 1: Fetch-Execute Cycle

F-E Stage 1 Fetch:

  • Contents of Program Counter/PC transferred to Memory Address Register/MAR
  • Reject: If implied the instruction is stored in the PC
  • Address bus used to transfer this address to main memory
  • Read signal sent along control bus
  • Transfer of main memory content uses the data bus
  • Contents of addressed memory location loaded into the Memory Buffer Register/MBR
  • Increment (contents of) Program Counter/PC Acceptable: At any part of fetch process after transferring PC to MAR
  • Increment Program Counter/PC and fetch instruction simultaneously
  • Contents of MBR copied to CIR

F-E Stage 2 Decode:

  • Instruction to decode held by the (Current) Instruction Register/(C)IR
  • The control unit decodes the instruction
  • Instruction split into opcode and operand(s)

F-E Stage 3 Execute:

  • If necessary, data is fetched/stored
  • The opcode identifies the type of operation/instruction to be performed (by the processor)
  • The operation (identified by the opcode) is performed by the control unit.
  • ALU used for calculation/comparisons
  • Result (may be) stored in register/main memory Acceptable: accumulator
  • Status register updated
  • If jump/branch required Program Counter/PC is updated
  • Control bus will transfer signals to other components to initiate/sequence actions

A good level of understanding would be demonstrated by a response that effectively covered all three stages of the cycle and did not focus excessively on one particular stage. There may be omissions, but these would not be of any key points. Any errors made would be minor.

Area 2: Improving Hardware

  • Replace the processor with one which has more cores Acceptable: Increase number of cores
  • Replace the processor with one which has more cache memory // increase the amount of cache memory // add cache memory
  • Increase clock speed of processor // replace the processor with one which runs at a faster clock speed Not enough: faster processor
  • Use a parallel processor architecture // use more processors which can work in parallel
  • Use a processor with a bigger word size
  • Use a processor that makes (better) use of pipelining
  • Install more RAM // main memory // primary memory
  • Use RAM // main memory // primary memory with a faster access time
  • Replace the motherboard with one which has buses which run at a faster clock speed Acceptable: increase bus clock speed
  • Replace the motherboard with one which has more lines in data bus Acceptable: increase number of lines in data bus
  • Acceptable: Replace HDDs with SSDs // replace HDDS with HDDs that can read data at a faster rate // replace SSDS with SSDs that can read data at a faster rate
  • Acceptable: Use the Harvard architecture instead of the von Neumann architecture

A good level of understanding would be demonstrated by a response that covered a range of hardware improvements that could be made (eg to the processor, buses, main memory) and did not focus excessively on only one component. Explanations of how a change would improve performance could be taken into account when considering how good the understanding is.

A-Level2020June3.4openDiagram2 marks

The diagram in Figure 2 describes the fetch part of the Fetch-Execute cycle. Some of the names of registers have been omitted from the figure and replaced with the numbers ① to ②.

State the full names of the registers that should appear in the diagram where the numbers are.

NumberRegister Name
Memory Address Register NE. MAR
Program Counter NE. PC
Current Instruction Register NE. CIR, IR A. Instruction Register

1 mark: Two registers correctly named OR

2 marks: All three registers correctly named

If student has used initialisms instead of full register names (or a mixture of both) then award 1 mark if all three registers are given the correct abbreviated name.

A-Level2019June5open12 marks

A student has written a computer program using an imperative high-level programming language. The program could be translated using either a compiler or an interpreter.

Describe the steps that must be completed to translate and execute the program.

Your description should include:

  • why translation is necessary
  • the differences between how a compiler and an interpreter would translate the program
  • how the machine code instructions that are used to carry out the program will be fetched and executed by the processor from main memory.
LevelDescriptionMark Range
4A line of reasoning has been followed to produce a coherent, relevant, substantiated and logically structured response. The response covers all three areas indicated in the guidance below and in at least two of these areas there is sufficient detail to show that the student has a good level of understanding. To reach the top of this mark range, a good level of understanding must be shown of all three areas.10-12
3A line of reasoning has been followed to produce a coherent, relevant, substantiated and logically structured response which shows a good level of understanding of at least two areas indicated in the guidance below.7-9
2A limited attempt has been made to follow a line of reasoning and the response has a mostly logical structure. Either a good level of understanding of one area from the guidance has been shown or a limited understanding of two areas.4-6
1A few relevant points have been made but there is no evidence that a line of reasoning has been followed. The points may only relate to one or two of the areas from the guidance or may be made in a superficial way with little substantiation.1-3

Guidance – Indicative Response

1. Why translation is necessary

  • Processor can only execute machine code instructions A. computer for processor
  • High-level instructions cannot be executed directly // high-level instructions are not machine code A. must be converted to machine code to be executed
  • NE. "Understand" for "execute".
  • Good level of understanding = at least one point made

2. Differences between compilation and interpreting

  • Compiler analyses program as a whole
  • Interpreter analyses program on a line-by-line basis
  • Compiler produces object code/executable file/machine code/bytecode
  • Interpreter calls subroutines within its own code to carry out commands
  • Compiler will not translate any of the program if it encounters an error
  • Interpreter translates/executes program until first error is encountered
  • If (unchanged) program executed twice/multiple times, compiler will only need to translate it once
  • Interpreter translates a program each time it is executed
  • Interpreter executes each line immediately after translating it
  • If student has written about compiler outputting bytecode then: bytecode will later be interpreted // executed by a virtual machine // just-in-time-compiled
  • Once translated, compiled code does not need the compiler to be present to run
  • An interpreter must always be present for a program that is interpreted to run
  • Once compiled, code will only run on one type of processor / virtual machine
  • Interpreter could translate the same instruction multiple times (eg if it is in a loop)
  • Good level of understanding = at least four points made

3. How machine code instructions fetched and executed

F-E Stage 1 Fetch:

  • Contents of Program Counter / PC transferred to Memory Address Register / MAR
  • R. if implied the instruction is stored in the PC
  • Address bus used to transfer this address to main memory
  • Transfer of main memory content uses the data bus
  • Contents of addressed memory location loaded into the Memory Buffer Register / MBR
  • Increment (contents of) Program Counter / PC A. at any part of fetch process after transferring PC to MAR
  • Increment Program Counter / PC and fetch instruction simultaneously
  • Contents of MBR copied to CIR

F-E Stage 2 Decode:

  • Decode instruction held by the (Current) Instruction Register / (C)IR
  • The control unit decodes the instruction
  • Instruction split into opcode and operand

F-E Stage 3 Execute:

  • If necessary, data is fetched
  • If necessary, data is stored in memory
  • The opcode identifies the type of operation/instruction to be performed (by the processor)
  • Result (may be) stored in register/accumulator
  • The operation (identified by the opcode) is performed by the processor. A. ALU
  • Status register updated
  • If jump / branch required Program Counter/PC is updated

General:

  • Instructions will be for program (if compiled) or interpreter (if interpreted)
  • Good level of understanding = at least five points made and at least two of the three stages of the F-E cycle are covered.
A-Level2017June1.1openDiagram4 marks

Describe how an instruction is fetched from main memory during the fetch stage of the fetch-execute cycle.

Your description should cover the use of registers and buses, together with the role of main memory.

LevelDescriptionMark Range
4Description covers all, or almost all, of the points in the indicative guidance and fully reflects the sequence in which steps occur. It includes use of registers, buses and main memory. An excellent level of understanding is shown with no misconceptions.4
3Description covers most (ie more than half) of the points in the indicative guidance and completely or almost completely reflects the correct sequence in which steps occur. At least two of the use of registers, buses and main memory are covered. A good level of understanding is shown. Whilst there may be some omissions, there is at most one misconception in the response.3
2At least two correct points are made from the indicative guidance and there is some indication of understanding of the correct sequence. Some understanding is shown.2
1At least one relevant point has been made. There is not sufficient evidence to conclude that the cycle has been understood.1

Guidance – Indicative Response

  • Contents of Program Counter/PC transferred to Memory Address Register/MAR
  • Address bus used to transfer this address to main memory
  • Fetched value/instruction transferred using the data bus
  • Contents of addressed memory location loaded into the Memory Buffer Register/MBR
  • Transfer content of Memory Buffer Register/MBR to the Current Instruction Register/CIR

A. Memory Data Register / MDR for MBR

I. Incrementing of program counter, even if incorrect

NE. Points made using register transfer notation only eg CIR ← [MBR]

A-Level2017June1.2openDiagram2 marks

During the decode and execute stages of the fetch-execute cycle the instruction that is being processed is stored in the CIR. Explain why the instruction could not be processed directly from the MBR.

To execute/carry out the instruction other data may need to be fetched (from main memory);

A. During execute phase MBR used to store other data

A. Further instructions may need to be fetched before the instruction has finished executing, if pipelining/parallelisation is referenced explicitly in the response

Further memory fetches would overwrite the contents of the MBR // the instruction would be overwritten by further memory fetches // writing the result of executing the instruction back to main memory would overwrite the instruction / MBR contents;

A. MBR is not (directly) wired to the (processor) components that will execute the instruction which CIR is

A. The MBR is not (directly) wired to the ALU as BOD

R. The MBR cannot decode instructions